![COA [Module 04 - Lecture 10]: Page Replacement Algorithms](/vi/Oho3QU-7pB8/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLBhG7E9aE5L7pw2lEwQZRz4GTa4Bg)
Computer Organization and Architecture NPTEL IITG
COA [Module 04 - Lecture 10]: Page Replacement Algorithms
1:21:21
![COA [Module 04 - Lecture 9]: Cache Indexing and Tagging Variations, Demand Paging](/vi/i5jVP9A0R6U/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLA9PvJ7IKObGUdJmqWqWqLQl-qpng)
Computer Organization and Architecture NPTEL IITG
COA [Module 04 - Lecture 9]: Cache Indexing and Tagging Variations, Demand Paging
1:34:00
![COA [Module 04 - Lecture 11]: Page Frame Allocation and Thrashing](/vi/K5QzAv1xF6M/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLAzcRK85Kk0V_2T8aW3fykFvvjT8g)
Computer Organization and Architecture NPTEL IITG
COA [Module 04 - Lecture 11]: Page Frame Allocation and Thrashing
39:48
![COA [Module 04 - Lecture 08]: TLBs and Page Fault Handling](/vi/8MXoZHAD-iU/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLBgn9KMh8x9jk28v_yAS7UyaXn7Vg)
Computer Organization and Architecture NPTEL IITG
COA [Module 04 - Lecture 08]: TLBs and Page Fault Handling
48:23
![COA [Module 04 - Lecture 07]: Paging and Segmentation](/vi/oXq3XiIOVgQ/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLB3i7B3kyV0i8zypQCykX7Iydlmfw)
Computer Organization and Architecture NPTEL IITG
COA [Module 04 - Lecture 07]: Paging and Segmentation
1:02:06
![COA [Module 04 - Lecture 06]: Basics of Virtual Memory and Address Translation](/vi/UuXFtqHC2ac/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLCTIfMLnjkERJMVfcI4ZDe64ggFFA)
Computer Organization and Architecture NPTEL IITG
COA [Module 04 - Lecture 06]: Basics of Virtual Memory and Address Translation
50:57
![COA [Module 04 - Lecture 12]: Summary](/vi/Rb8UhXnJZFQ/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLB5qll1ZmAink8CLn8t6Q39B4Pu5Q)
Computer Organization and Architecture NPTEL IITG
COA [Module 04 - Lecture 12]: Summary
9:58
![COA [Module 04 - Lecture 04]: Associative and Multi-level Caches](/vi/XZF4khqXmNI/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLDNLfCf-0gCRK6Plsz8WvlngRrywg)
Computer Organization and Architecture NPTEL IITG
COA [Module 04 - Lecture 04]: Associative and Multi-level Caches
53:08
![COA [Module 04 - Lecture 03]: Direct-mapped Caches: Misses, Writes and Performance](/vi/YYrGbJ-SRpc/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLBfuFsZrJjQt_Hgmah8GEU0gSaTIA)
Computer Organization and Architecture NPTEL IITG
COA [Module 04 - Lecture 03]: Direct-mapped Caches: Misses, Writes and Performance
45:52
![COA [Module 04 - Lecture 05]: Summary](/vi/44tdrpyUIZA/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLBTaLBK8gWOjE6p1QB2C6gucZZHUg)
Computer Organization and Architecture NPTEL IITG
COA [Module 04 - Lecture 05]: Summary
23:13
![COA [Module 04 - Lecture 02]: Basics of Memory and Cache (Part-2)](/vi/k95DzZESypU/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLCEXDAczwD66YRlBjGHI1TxDLhwZA)
Computer Organization and Architecture NPTEL IITG
COA [Module 04 - Lecture 02]: Basics of Memory and Cache (Part-2)
36:05
![COA [Module 04 - Lecture 01]: Basics of Memory and Cache (Part-1)](/vi/YHfulm7Tubg/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLCkIqd7f1ZSMO3U7rP-Vfm035FbmA)
Computer Organization and Architecture NPTEL IITG
COA [Module 04 - Lecture 01]: Basics of Memory and Cache (Part-1)
16:38
![COA [Module 05 - Lecture 04]: Storage Devices](/vi/MhNm-c1JVPg/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLA9V2JJqefFW9aaZfzD5ShyZrEpSA)
Computer Organization and Architecture NPTEL IITG
COA [Module 05 - Lecture 04]: Storage Devices
1:08:46
![COA [Module 05 - Lecture 03]: DMA Transfer](/vi/CSkN0wj0zZU/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLB3FzjFgOJkk7-nsjEwUB0EkP1ehw)
Computer Organization and Architecture NPTEL IITG
COA [Module 05 - Lecture 03]: DMA Transfer
49:19
![COA [Module 05 - Lecture 02]: Interrupt Driven I/O](/vi/Ro70ySbJzv8/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLC-A0Z8sjy9jbQQOO4UcRhue612Gg)
Computer Organization and Architecture NPTEL IITG
COA [Module 05 - Lecture 02]: Interrupt Driven I/O
1:03:06
![COA [Module 05 - Lecture 01]: Input/Output Primitives](/vi/JxVQ3MqLnZw/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLBkfROQ3lzmUvosOYm_DptEZHobdw)
Computer Organization and Architecture NPTEL IITG
COA [Module 05 - Lecture 01]: Input/Output Primitives
1:01:29
![COA [Module 03 - Lecture 08]: Organization and Optimization of Microprogrammed Control unit](/vi/lKQfg96D408/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLCBigs_FEW1aDXFoVIpK0JZgEkLBQ)
Computer Organization and Architecture NPTEL IITG
COA [Module 03 - Lecture 08]: Organization and Optimization of Microprogrammed Control unit
1:16:43
![COA [Module 03 - Lecture 07]: Microinstructions and Microprograms](/vi/UMqHq_9omr0/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLApZzoydIETU9CeUVOiK5RBDv56YA)
Computer Organization and Architecture NPTEL IITG
COA [Module 03 - Lecture 07]: Microinstructions and Microprograms
1:09:05
![COA [Module 03 - Lecture 09]: Different Internal CPU Bus Organization](/vi/iaWX3Au19zo/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLDD2dZhAfmNX2oE3V9y03TXh_idQg)
Computer Organization and Architecture NPTEL IITG
COA [Module 03 - Lecture 09]: Different Internal CPU Bus Organization
1:02:19
![COA [Module 03 - Lecture 06]: Design of Hardwired controlled Control Unit](/vi/b5thcNYBrQc/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLDnnloEqLaYuF_GJwt8vDy91NJ0WQ)
Computer Organization and Architecture NPTEL IITG
COA [Module 03 - Lecture 06]: Design of Hardwired controlled Control Unit
46:49
![COA [Module 03 - Lecture 05]: Handling Control Transfer Instructions](/vi/ikrJ5ErIX08/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLAG8jmf0y14aGQOKvlOQquAX7SkOQ)
Computer Organization and Architecture NPTEL IITG
COA [Module 03 - Lecture 05]: Handling Control Transfer Instructions
46:57
![COA [Module 03 - Lecture 02]: Control Signals and Timing Sequence](/vi/LNLjGgsDjBk/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLC12WuKEG3F7p6QX5ZeRrkt4PoWhA)
Computer Organization and Architecture NPTEL IITG
COA [Module 03 - Lecture 02]: Control Signals and Timing Sequence
53:17
![COA [Module 03 - Lecture 01]: Instruction Cycle and Micro-operations](/vi/L2SLS9FgTx0/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLCleg7uE4ji0uMVUPJxpNSqVX0JXA)
Computer Organization and Architecture NPTEL IITG
COA [Module 03 - Lecture 01]: Instruction Cycle and Micro-operations
50:29
![COA [Module 03 - Lecture 03]: Control Signals for Complete Instruction Execution](/vi/KvjmIpOYn4o/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLBJ1KvKaE_UogOha0VESXer8Q8sWw)
Computer Organization and Architecture NPTEL IITG
COA [Module 03 - Lecture 03]: Control Signals for Complete Instruction Execution
46:01
![COA [Module 03 - Lecture 04]: Handling Different Addressing Modes](/vi/vrZmX3VsZ-A/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLAWCa77MbdfztfSBaW_ek1S69Jwhg)
Computer Organization and Architecture NPTEL IITG
COA [Module 03 - Lecture 04]: Handling Different Addressing Modes
33:26
![COA [Module 02 - Lecture 07]: Flags and Conditional Instructions](/vi/t4mzLPvv1yQ/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLCs9HFvfeUqpjP_Pq2emeQyz6cYRw)
Computer Organization and Architecture NPTEL IITG
COA [Module 02 - Lecture 07]: Flags and Conditional Instructions
55:59
![COA [Module 02 - Lecture 08]: Instruction: Procedure CALL/RETURN](/vi/bGFgMK9qz00/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLBfMnd4JtauiHHSKEnb5OeZjXvBHQ)
Computer Organization and Architecture NPTEL IITG
COA [Module 02 - Lecture 08]: Instruction: Procedure CALL/RETURN
43:06
![COA [Module 02 - Lecture 06]: Addressing Modes](/vi/k_QgyvsqtwA/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLBEFup65KXcgTuU7sJBcq-nKTWS2Q)
Computer Organization and Architecture NPTEL IITG
COA [Module 02 - Lecture 06]: Addressing Modes
58:51
![COA [Module 02 - Lecture 04]: Instruction Format](/vi/H7QrDhPFwIA/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLCCNuMCaiXm_7tS0lh52uNG-yRAaw)
Computer Organization and Architecture NPTEL IITG
COA [Module 02 - Lecture 04]: Instruction Format
49:40
![COA [Module 02 - Lecture 05]: Instruction Set](/vi/BEvWyiDu4x4/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLC_gllJQ21Ig6b-YUTTYyIpKrs7qw)
Computer Organization and Architecture NPTEL IITG
COA [Module 02 - Lecture 05]: Instruction Set
37:15
![COA [Module 02 - Lecture 01]: Components of Central Processing Unit (CPU) and External Interface](/vi/fvtOGHXqYBs/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLCm8zJkfRP3d_K9lMI2AnLjSppDZw)
Computer Organization and Architecture NPTEL IITG
COA [Module 02 - Lecture 01]: Components of Central Processing Unit (CPU) and External Interface
55:54
![COA [Module 02 - Lecture 03]: Instruction Execution](/vi/HfPS8DCzxEE/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLCnG7hEn4b97JB-Ep6TUYbHaoxaEw)
Computer Organization and Architecture NPTEL IITG
COA [Module 02 - Lecture 03]: Instruction Execution
48:46
![COA [Module 02 - Lecture 02]: Main Memory](/vi/af3lB04RInQ/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLDtY5ydLR10JShH9JGN64QPmaa-Gw)
Computer Organization and Architecture NPTEL IITG
COA [Module 02 - Lecture 02]: Main Memory
42:59
![COA [Module 01 - Lecture 02]: Digital Logic Building Blocks](/vi/_dHOOFI2VzE/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLDjULsdo6z4wKINTN2tKPQjL8HYtA)
Computer Organization and Architecture NPTEL IITG
COA [Module 01 - Lecture 02]: Digital Logic Building Blocks
1:21:52
![COA [Module 01 - Lecture 06]: Execution of Program and Programming Languages](/vi/WgTAUZ58jEY/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLDggu0tUyB3mAqwzsO-O3CZZn4ikg)
Computer Organization and Architecture NPTEL IITG
COA [Module 01 - Lecture 06]: Execution of Program and Programming Languages
1:14:52
![COA [Module 01 - Lecture 04]: Basic Elements of Processor](/vi/pGQ69Y60tvA/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLCVAtdTyjSC3sEMNCvpjjd6tat8pg)
Computer Organization and Architecture NPTEL IITG
COA [Module 01 - Lecture 04]: Basic Elements of Processor
1:02:39
![COA [Module 01 - Lecture 05]: Storage and I/O Interface](/vi/cipkWLPAsKE/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLAhovWlPdS-eACs52hG4leo7GYt9g)
Computer Organization and Architecture NPTEL IITG
COA [Module 01 - Lecture 05]: Storage and I/O Interface
48:51
![COA [Module 01 - Lecture 03]: Information Representation and Number Systems](/vi/J4Z4C3oHi18/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLCsy8lr9YgqCXYw0KiZn76aG-lvsQ)
Computer Organization and Architecture NPTEL IITG
COA [Module 01 - Lecture 03]: Information Representation and Number Systems
1:17:21
![COA [Module 01 - Lecture 01]: Model of Computer and Working Principle](/vi/msqxkEKFg8I/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLBuQI3-mlnlZPJ2b5x8-ZKV564mQA)
Computer Organization and Architecture NPTEL IITG
COA [Module 01 - Lecture 01]: Model of Computer and Working Principle
1:19:01
Computer Organization and Architecture NPTEL IITG
Introduction
5:40