Back To Basics
Shorts and Opens in Physical Design
0:22
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Routing | Physical Design | Back To Basics
11:08
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SPEF File | Physical Design | Back To Basics
16:22
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Clock Tree Synthesis | Physical Design | Back To Basics
11:41
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Placement | Physical Design | Back To Basics
10:41
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Floorplanning | Physical Design | Back To Basics
16:12
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Synthesis | RTL2GDSII | Back To Basics
13:15
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Propagation Delay | Slew | Skew | STA | Back To Basics
9:21
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Static Timing Analysis | STA | Back To Basics
7:35
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Power Dissipation in CMOS Circuits | Back To Basics
7:50
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Reading Timing Reports | STA | Physical Design | Back To Basics
15:47
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Multicycle Paths | STA | Back To Basics
5:33
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Can Set Up and Hold Time be negative? | STA | Back To Basics
10:42
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Hold Time | STA | Back To Basics
8:57
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Set Up Time | STA | Back To Basics
7:55
Back To Basics
D-Latch & D-Flip flop.
8:28
Back To Basics
Antenna Effects | Physical Verification | Back To Basics
13:00
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Working of a MOSFET
9:23
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Filler Cells | Physical Design
4:55
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What are Decap Cells | Physical Design
6:14
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What are Tie Cells | Physical Design
5:24
Back To Basics
What are Well Tap Cells | Physical Design
5:20