GNURadio 3.10 on Ubuntu 22 in VirtualBox
Peter Mathys
GNURadio 3.10 on Ubuntu 22 in VirtualBox
1:14:01
Setup VirtualBox and Install Ubuntu 22.04
Peter Mathys
Setup VirtualBox and Install Ubuntu 22.04
36:26
Installing Miniconda And Complex Exponentials Examples in Jupyter Notebook
Peter Mathys
Installing Miniconda And Complex Exponentials Examples in Jupyter Notebook
51:06
Sampling Theorem - Graphical Derivation
Peter Mathys
Sampling Theorem - Graphical Derivation
46:28
Soldering 101
Peter Mathys
Soldering 101
6:10
Analog Discovery 2: Flywire Assembly vs BNC Adapter
Peter Mathys
Analog Discovery 2: Flywire Assembly vs BNC Adapter
13:50
Analog Discovery 2 and WaveForms: A First Measurement
Peter Mathys
Analog Discovery 2 and WaveForms: A First Measurement
9:35
Fractional Number Conversions
Peter Mathys
Fractional Number Conversions
31:17
Decimal to Binary and Others Conversion
Peter Mathys
Decimal to Binary and Others Conversion
27:49
Fractional Number Representation
Peter Mathys
Fractional Number Representation
14:55
Number Systems with Radix r
Peter Mathys
Number Systems with Radix r
13:08
BPSK Signal in GNU Radio Companion
Peter Mathys
BPSK Signal in GNU Radio Companion
1:19
GNU Radio: Pulse Amplitude Modulation with Noise (Matched Filter)
Peter Mathys
GNU Radio: Pulse Amplitude Modulation with Noise (Matched Filter)
0:21
GNU Radio: Pulse Amplitude Modulation with Noise (Impulse Sampling)
Peter Mathys
GNU Radio: Pulse Amplitude Modulation with Noise (Impulse Sampling)
0:21
GNU Radio: Pulse Amplitude Modulation
Peter Mathys
GNU Radio: Pulse Amplitude Modulation
0:22
Intro to Verilog and ModelSim, Part2
Peter Mathys
Intro to Verilog and ModelSim, Part2
17:41
Intro to Verilog and ModelSim, Part1
Peter Mathys
Intro to Verilog and ModelSim, Part1
30:23
Counter Design Using FSM Approach
Peter Mathys
Counter Design Using FSM Approach
20:30
State Minimization, Part2
Peter Mathys
State Minimization, Part2
23:12
State Minimization, Part1
Peter Mathys
State Minimization, Part1
16:41
BCD Adder in Verilog
Peter Mathys
BCD Adder in Verilog
37:41
Prime Implicants and More
Peter Mathys
Prime Implicants and More
30:55
NAND/NOR Only Example
Peter Mathys
NAND/NOR Only Example
14:30
Boolean Algebra Example
Peter Mathys
Boolean Algebra Example
24:54
Boolean Identity Proofs
Peter Mathys
Boolean Identity Proofs
15:20
Decimal To Binary And Hexadecimal
Peter Mathys
Decimal To Binary And Hexadecimal
19:29
Finite State Machines in Verilog
Peter Mathys
Finite State Machines in Verilog
34:50
Verilog for Registers and Counters
Peter Mathys
Verilog for Registers and Counters
25:05
Fast Adders, Part1
Peter Mathys
Fast Adders, Part1
22:02
Arithmetic Circuits in Verilog, Part 2
Peter Mathys
Arithmetic Circuits in Verilog, Part 2
40:17
Arithmetic Circuits In Verilog, Part1
Peter Mathys
Arithmetic Circuits In Verilog, Part1
36:40
Fast Adders, Part2
Peter Mathys
Fast Adders, Part2
17:45
IntroductionToVerilog Part2
Peter Mathys
IntroductionToVerilog Part2
27:30
Introduction to Verilog Part 1
Peter Mathys
Introduction to Verilog Part 1
24:11
AC to DC Conversion
Peter Mathys
AC to DC Conversion
21:24
Transformers
Peter Mathys
Transformers
12:39
CMOS Gate Implementations
Peter Mathys
CMOS Gate Implementations
18:44
CMOS Transistors
Peter Mathys
CMOS Transistors
29:26
Multiplexers
Peter Mathys
Multiplexers
10:52
Different Types Of Flip-Flops
Peter Mathys
Different Types Of Flip-Flops
19:35
From Latches To Flip-Flops
Peter Mathys
From Latches To Flip-Flops
32:06
Hours Counter (1-12) For Clock
Peter Mathys
Hours Counter (1-12) For Clock
2:04
Karnaugh Map Examples
Peter Mathys
Karnaugh Map Examples
41:42
BooleanAlgebra
Peter Mathys
BooleanAlgebra
31:51
SOPandPOS
Peter Mathys
SOPandPOS
14:53
AM Radio in Action
Peter Mathys
AM Radio in Action
1:09
TransistorsII
Peter Mathys
TransistorsII
14:15
RRC Filter, System Function
Peter Mathys
RRC Filter, System Function
10:13
Capacitors 012214
Peter Mathys
Capacitors 012214
30:45
First Multisim Tutorial
Peter Mathys
First Multisim Tutorial
5:11
fsk21c_edit2.mpg
Peter Mathys
fsk21c_edit2.mpg
0:06