#demonstration of #halfadder #lec8 #part3
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#demonstration of #halfadder #lec8 #part3
23:42
#Level #of #abstration in #veriloghdl #lec7 #part2
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#Level #of #abstration in #veriloghdl #lec7 #part2
18:59
#module syntax in #veriloghdl #lec6 #part1
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#module syntax in #veriloghdl #lec6 #part1
21:29
concept of #module in #verilog #lec5
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concept of #module in #verilog #lec5
13:37
DIFFRENCE between #verilog vs #vhdl vs #c language #Lec4
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DIFFRENCE between #verilog vs #vhdl vs #c language #Lec4
14:15
introduction of #verilog #HDL? #lec3
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introduction of #verilog #HDL? #lec3
17:14
Syllabus overview #verilog #lec2
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Syllabus overview #verilog #lec2
8:54
Importance of #verilog #lec1
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Importance of #verilog #lec1
16:22
free Verilog simulator Icarus Verilog and Aldec riviera #part0
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free Verilog simulator Icarus Verilog and Aldec riviera #part0
18:46
#design of 3 input #majority #function using 4:1 #mux #lec11
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#design of 3 input #majority #function using 4:1 #mux #lec11
14:57
#AOI #and-orgate implementationof#2*1 mux #lec10
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#AOI #and-orgate implementationof#2*1 mux #lec10
10:29
#design #xor #xnor using #multiplexer #lec9 #part3
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#design #xor #xnor using #multiplexer #lec9 #part3
9:27
#design of #nandgate #nor using #multiplexer #lec8 #part2
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#design of #nandgate #nor using #multiplexer #lec8 #part2
7:52
#design of #logicgate using #multiplexer #lec7 #part1
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#design of #logicgate using #multiplexer #lec7 #part1
13:01
#design of xor xnor using #minimum number of #norgate #lec6
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#design of xor xnor using #minimum number of #norgate #lec6
9:58
#design of #AND #OR #NAND USING #norgate #lec5
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#design of #AND #OR #NAND USING #norgate #lec5
8:00
#design xor & xnor gate using #nandgate #lec4
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#design xor & xnor gate using #nandgate #lec4
7:21
#design of #and #norgate #orgate using #nandgate #lec3
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#design of #and #norgate #orgate using #nandgate #lec3
11:11
#universalgate #nandgate #norgate #lec2
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#universalgate #nandgate #norgate #lec2
6:41
#design of 3 input & 4 input #NAND using 2 input #nandgate #lec1
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#design of 3 input & 4 input #NAND using 2 input #nandgate #lec1
7:02
#c code for #decimal to #binary conversion #part14
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#c code for #decimal to #binary conversion #part14
15:17
program to #sorting array (Bubble sort) #part13
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program to #sorting array (Bubble sort) #part13
17:22
#c program to print multiplication #table #part12
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#c program to print multiplication #table #part12
8:23
#cmos COURSE OVERVIEW inv-0 #part15
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#cmos COURSE OVERVIEW inv-0 #part15
6:29
#c program to print #fibonacci series #part11
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#c program to print #fibonacci series #part11
13:33
DESIGN of #fulladder USING #nandgate and also #verilogcode #part3
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DESIGN of #fulladder USING #nandgate and also #verilogcode #part3
11:41
#design of #fulladder using #halfadder #part2
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#design of #fulladder using #halfadder #part2
11:01
design of #halfadder using #nandgate #verilogcode #part1
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design of #halfadder using #nandgate #verilogcode #part1
11:01
#SUM of digit of number #part10
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#SUM of digit of number #part10
11:25
#placement syllabus for #analog #digital #part2
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#placement syllabus for #analog #digital #part2
10:12
#armstrongnumber #part9
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#armstrongnumber #part9
13:39
#palindromenumber #part8
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#palindromenumber #part8
15:45
what should do in #mtech #1st #semester #CGPA or #placement #part1
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what should do in #mtech #1st #semester #CGPA or #placement #part1
15:01
#reverse of number #part7
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#reverse of number #part7
14:16
#primenumber #part6
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#primenumber #part6
14:21
#swap of two number without 3rd variables #part5
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#swap of two number without 3rd variables #part5
6:40
#swap of two number using 3rd variables #part4
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#swap of two number using 3rd variables #part4
7:43
interview question overview #part3.1
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interview question overview #part3.1
2:10
#gate leakage #part14
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#gate leakage #part14
7:29
#substrate Leakage #part13
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#substrate Leakage #part13
7:26
#subthreshold slope #part12
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#subthreshold slope #part12
9:55
#Subthreshold leakage #part11
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#Subthreshold leakage #part11
8:29
DRAIN INDUCED BARRIER LOWERING #DIBL #part10
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DRAIN INDUCED BARRIER LOWERING #DIBL #part10
12:19
#velocitysaturation #part9
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#velocitysaturation #part9
11:45
#channel length modulation #part8
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#channel length modulation #part8
21:03
#bodyeffect #part7
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#bodyeffect #part7
14:51
current equation in nmos/pmos #part6
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current equation in nmos/pmos #part6
15:51
construction of n-channel (nmos) #part5
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construction of n-channel (nmos) #part5
27:18
construction of n-channel depletion mosfet #part4
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construction of n-channel depletion mosfet #part4
33:53
2'S complement using #fsm design with DFF #part7
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2'S complement using #fsm design with DFF #part7
13:15
forward and reverse biased #part3
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forward and reverse biased #part3
5:38
PN Junction #part2
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PN Junction #part2
18:46
BASIC semiconductor physics #part1
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BASIC semiconductor physics #part1
25:33
#overlaping using #mealy 1011 #part6
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#overlaping using #mealy 1011 #part6
7:52
course overview #part0
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course overview #part0
9:22
non overlaping 1011 using #mealymachine #part5
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non overlaping 1011 using #mealymachine #part5
12:12
overlaping 1010 using moore #part4
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overlaping 1010 using moore #part4
12:34
non overlaping moore 1010 #part3
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non overlaping moore 1010 #part3
17:13
execution process #part3
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execution process #part3
9:55
#translator compiler vs interpreter #part2
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#translator compiler vs interpreter #part2
11:10
introduction of c language #part1
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introduction of c language #part1
9:51
Mealy vs Moore Machine #part2
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Mealy vs Moore Machine #part2
6:39
introduction of sequence detector #part1
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introduction of sequence detector #part1
10:24
#datatype #part8
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#datatype #part8
9:12
Level of abstration #part7
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Level of abstration #part7
11:20
#identifier #part6
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#identifier #part6
4:02
concept of #module #keyword #part5
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concept of #module #keyword #part5
10:08
course overview #part4
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course overview #part4
5:30
verilog vs c #part3 #install xillinx vivado
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verilog vs c #part3 #install xillinx vivado
7:34
verilog vs VHDL #part2
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verilog vs VHDL #part2
3:18
Introduction of Verilog #part1
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Introduction of Verilog #part1
13:29
frequency multiplier f=2fin #part7
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frequency multiplier f=2fin #part7
5:31
frequency divider 2/3fin #part6
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frequency divider 2/3fin #part6
8:36
Digital electronics revision #part1
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Digital electronics revision #part1
20:44
frequency divider f/2 using D_FF #part5 #50percentage #25% #75%
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frequency divider f/2 using D_FF #part5 #50percentage #25% #75%
13:48
frequency divider f/5 #part4 with #50cent
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frequency divider f/5 #part4 with #50cent
15:33
frequency divide f/3 #part3 with #33% ,50% #dutycycle
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frequency divide f/3 #part3 with #33% ,50% #dutycycle
9:31
frequency divider part2#interviewquestions
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frequency divider part2#interviewquestions
11:15
frequency divider #part1
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frequency divider #part1
16:23
frequency divider #part0
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frequency divider #part0
11:06
Negative Edge detection part- 2 By- chandan kr.
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Negative Edge detection part- 2 By- chandan kr.
6:38
EDGE DETECTION CIRCUIT- PART 1.chandan kr
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EDGE DETECTION CIRCUIT- PART 1.chandan kr
6:05