Crosstalk Delta report Analysis | Noise analysis
Jairam Gouda
Crosstalk Delta report Analysis | Noise analysis
9:18
Understanding report_delay_calculation | Delay Calculation
Jairam Gouda
Understanding report_delay_calculation | Delay Calculation
8:12
Graph Based Analysis vs Path Based Analysis | Types of PBA
Jairam Gouda
Graph Based Analysis vs Path Based Analysis | Types of PBA
7:58
Understanding Timing Reports
Jairam Gouda
Understanding Timing Reports
23:46
17. 8T SRAM Cell | Integrated Circuit Memory
Jairam Gouda
17. 8T SRAM Cell | Integrated Circuit Memory
7:18
16. 7T SRAM Cell | Integrated Circuit Memories
Jairam Gouda
16. 7T SRAM Cell | Integrated Circuit Memories
4:36
15. SRAM Cell Stability | Integrated Circuit Memories
Jairam Gouda
15. SRAM Cell Stability | Integrated Circuit Memories
16:42
Design Technology Co-optimization (DTCO) | VLSI
Jairam Gouda
Design Technology Co-optimization (DTCO) | VLSI
12:02
14. 6T SRAM Cell Write Operation | Integrated Circuit Memory
Jairam Gouda
14. 6T SRAM Cell Write Operation | Integrated Circuit Memory
10:59
13. Read Operation of SRAM Cell | Integrated Circuit Memories
Jairam Gouda
13. Read Operation of SRAM Cell | Integrated Circuit Memories
9:23
12. Introduction to 6T SRAM cell | Integrated Circuit Memories
Jairam Gouda
12. Introduction to 6T SRAM cell | Integrated Circuit Memories
8:14
11. Memory Array Architecture | Integrated Circuit Memory
Jairam Gouda
11. Memory Array Architecture | Integrated Circuit Memory
6:14
10. Introduction to DRAM | Integrated Circuit Memory
Jairam Gouda
10. Introduction to DRAM | Integrated Circuit Memory
4:30
9. Introduction to SRAM | Integrated Circuit Memory
Jairam Gouda
9. Introduction to SRAM | Integrated Circuit Memory
4:21
8. Introduction to Read write memory | Integrated Circuit Memory
Jairam Gouda
8. Introduction to Read write memory | Integrated Circuit Memory
3:32
7. Flash Memory | Integrated Circuit Memory
Jairam Gouda
7. Flash Memory | Integrated Circuit Memory
7:33
6. Electrically Erasable Programmable ROM (EEPROM) | Integrated Circuit Memories
Jairam Gouda
6. Electrically Erasable Programmable ROM (EEPROM) | Integrated Circuit Memories
3:48
5. Erasable Programmable ROM (EPROM) | Integrated Circuit Memories
Jairam Gouda
5. Erasable Programmable ROM (EPROM) | Integrated Circuit Memories
5:01
4. Read Only Memory (ROM) | Integrated Circuit Memories
Jairam Gouda
4. Read Only Memory (ROM) | Integrated Circuit Memories
5:55
3. Classification of Memories | Integrated Circuit Memories
Jairam Gouda
3. Classification of Memories | Integrated Circuit Memories
7:22
2. Memory basics | Integrated Circuit Memories
Jairam Gouda
2. Memory basics | Integrated Circuit Memories
5:51
1. Introduction to Integrated Circuit Memories
Jairam Gouda
1. Introduction to Integrated Circuit Memories
6:32
Clock Reconvergence Pessimism Removal (CRPR) | STA
Jairam Gouda
Clock Reconvergence Pessimism Removal (CRPR) | STA
8:31
Pins, ports and interfaces | VLSI design
Jairam Gouda
Pins, ports and interfaces | VLSI design
9:05
Parasitic Extraction and Back Annotation | VLSI Physical Design
Jairam Gouda
Parasitic Extraction and Back Annotation | VLSI Physical Design
14:40
Concept of Mutex | Software and physical design (IR drop) perspective
Jairam Gouda
Concept of Mutex | Software and physical design (IR drop) perspective
9:47
Timing path | Slack or Margin and other terminologies
Jairam Gouda
Timing path | Slack or Margin and other terminologies
16:46
Timing Arc in STA | Delay calculation
Jairam Gouda
Timing Arc in STA | Delay calculation
10:16
STA in ASIC design flow | Accuracy of STA
Jairam Gouda
STA in ASIC design flow | Accuracy of STA
10:11
Basic terminologies in STA | Static timing analysis
Jairam Gouda
Basic terminologies in STA | Static timing analysis
9:35
Difference between STA and Dynamic timing analysis | STA vs DTA
Jairam Gouda
Difference between STA and Dynamic timing analysis | STA vs DTA
7:40
Introduction to Static Timing Analysis | STA , Physical Design, Synthesis in VLSI
Jairam Gouda
Introduction to Static Timing Analysis | STA , Physical Design, Synthesis in VLSI
10:01
What is overlay in Integrated Circuits ? | DFM
Jairam Gouda
What is overlay in Integrated Circuits ? | DFM
3:33
Design for Manufacturability (DFM ) | DRCs, Dummyfill
Jairam Gouda
Design for Manufacturability (DFM ) | DRCs, Dummyfill
14:12
Physical Design Flow | VLSI back end | IC Design
Jairam Gouda
Physical Design Flow | VLSI back end | IC Design
15:21
Emulation in VLSI | Functional Verification, Simulation, Formal Verification
Jairam Gouda
Emulation in VLSI | Functional Verification, Simulation, Formal Verification
12:21
Inputs to VLSI Physical Design | LEF, DEF, LIB, TLUP, netlist, SDC files
Jairam Gouda
Inputs to VLSI Physical Design | LEF, DEF, LIB, TLUP, netlist, SDC files
15:04
VLSI ASIC Design flow
Jairam Gouda
VLSI ASIC Design flow
10:28
Hierarchy, Regularity, Modularity and Locality | Structured Design Strategies in VLSI
Jairam Gouda
Hierarchy, Regularity, Modularity and Locality | Structured Design Strategies in VLSI
11:43
Design for Testability | An introduction to DFT
Jairam Gouda
Design for Testability | An introduction to DFT
7:24
Virtual Clock | Static Timing Analysis
Jairam Gouda
Virtual Clock | Static Timing Analysis
4:18
Strained Silicon - Part 2: Mobility Enhancement
Jairam Gouda
Strained Silicon - Part 2: Mobility Enhancement
8:45
Strained Silicon - Part 1: Understanding mobility
Jairam Gouda
Strained Silicon - Part 1: Understanding mobility
4:52
High-K and Low-K dielectrics in VLSI | IC manufacturing
Jairam Gouda
High-K and Low-K dielectrics in VLSI | IC manufacturing
7:37
Transition Frequency of MOS transistor and it's significance in VLSI
Jairam Gouda
Transition Frequency of MOS transistor and it's significance in VLSI
13:59
Libraries and Intellectual Properties in VLSI
Jairam Gouda
Libraries and Intellectual Properties in VLSI
8:49
Combinational Logic Hazards | Hazard free digital circuits
Jairam Gouda
Combinational Logic Hazards | Hazard free digital circuits
15:49
Sequential Circuit Models | Mealy and Moore Machine Models
Jairam Gouda
Sequential Circuit Models | Mealy and Moore Machine Models
19:01
What are SOCs and ASICs? | Difference between SOCs and ASICs
Jairam Gouda
What are SOCs and ASICs? | Difference between SOCs and ASICs
10:39
Metal Layer basics in VLSI
Jairam Gouda
Metal Layer basics in VLSI
12:35
Clock Skew and Clock Jitter
Jairam Gouda
Clock Skew and Clock Jitter
13:31
Antenna Effect in VLSI | How to fix antenna violations?
Jairam Gouda
Antenna Effect in VLSI | How to fix antenna violations?
9:50
Power Integrity and IR drop | Techniques to reduce IR drop
Jairam Gouda
Power Integrity and IR drop | Techniques to reduce IR drop
7:58
Power Gating and Mother/Daughter cells in VLSI
Jairam Gouda
Power Gating and Mother/Daughter cells in VLSI
12:33
Signal Integrity Issues in VLSI | Crosstalk, Glitch | How to avoid these issues?
Jairam Gouda
Signal Integrity Issues in VLSI | Crosstalk, Glitch | How to avoid these issues?
15:00
Setup time, Hold time and Metastability | What's the origin? Can these be negative?
Jairam Gouda
Setup time, Hold time and Metastability | What's the origin? Can these be negative?
21:55
Electromigration and Reliability in VLSI | Why do chips die?
Jairam Gouda
Electromigration and Reliability in VLSI | Why do chips die?
12:25
Buffer and Inverter insertion in Timing paths | Inverters vs Buffers | Buffer as a repeater
Jairam Gouda
Buffer and Inverter insertion in Timing paths | Inverters vs Buffers | Buffer as a repeater
12:25
Timing Classification of Digital Systems | Synchronous, Asynchronous, Mesochronous ....
Jairam Gouda
Timing Classification of Digital Systems | Synchronous, Asynchronous, Mesochronous ....
13:23
Understanding CMOS inverter | Why NMOS passes strong 0 and PMOS passes strong 1
Jairam Gouda
Understanding CMOS inverter | Why NMOS passes strong 0 and PMOS passes strong 1
7:53
Clock Gating | Integrated Clock Gating cell
Jairam Gouda
Clock Gating | Integrated Clock Gating cell
12:20
Challenges in 7nm/5nm/3nm CMOS fabrication process
Jairam Gouda
Challenges in 7nm/5nm/3nm CMOS fabrication process
9:14
Why do we use polysilicon gate in VLSI?
Jairam Gouda
Why do we use polysilicon gate in VLSI?
7:59
Why do we use multiple active contacts ?
Jairam Gouda
Why do we use multiple active contacts ?
3:48
Latch-Up phenomenon in CMOS circuits and Prevention Techniques
Jairam Gouda
Latch-Up phenomenon in CMOS circuits and Prevention Techniques
15:42
Automating calculations using .meas in LTspice | Measuring in LT spice
Jairam Gouda
Automating calculations using .meas in LTspice | Measuring in LT spice
8:15
Differential Amplifier with Active Load in LTspice
Jairam Gouda
Differential Amplifier with Active Load in LTspice
5:19
4. CS amplifier with current mirror load in LTspice
Jairam Gouda
4. CS amplifier with current mirror load in LTspice
6:16
3. CS Amplifier with Diode Connected Load in LTspice
Jairam Gouda
3. CS Amplifier with Diode Connected Load in LTspice
6:48
2. CS amplifier with Current Source Load in LTspice
Jairam Gouda
2. CS amplifier with Current Source Load in LTspice
9:55
1. CS Amplifier with Resistor Load in LTspice | Analog Electronics | Simulation
Jairam Gouda
1. CS Amplifier with Resistor Load in LTspice | Analog Electronics | Simulation
11:45
Full Bridge Rectifier using MOSFETs in LTspice
Jairam Gouda
Full Bridge Rectifier using MOSFETs in LTspice
5:32
CMOS Inverter Midpoint voltage - DC analysis | Including Libray | Using Parameters in LT spice
Jairam Gouda
CMOS Inverter Midpoint voltage - DC analysis | Including Libray | Using Parameters in LT spice
14:26
Full Bridge inverter in LT spice
Jairam Gouda
Full Bridge inverter in LT spice
3:31
Half bridge inverter in LT Spice
Jairam Gouda
Half bridge inverter in LT Spice
3:47
Inverting Amplifier using LM 741 Op-amp in LT spice
Jairam Gouda
Inverting Amplifier using LM 741 Op-amp in LT spice
7:11
PMOS V-I characteristics using LT spice
Jairam Gouda
PMOS V-I characteristics using LT spice
4:48
NMOS output characteristics in LTspice | LT spice simulation
Jairam Gouda
NMOS output characteristics in LTspice | LT spice simulation
4:22
NMOS input characteristics in LT Spice
Jairam Gouda
NMOS input characteristics in LT Spice
4:42
Customising LT spice | how to change background and colors in LT spice
Jairam Gouda
Customising LT spice | how to change background and colors in LT spice
4:41
Recording and playing audio using Matlab
Jairam Gouda
Recording and playing audio using Matlab
2:00
Designing helical antenna in Matlab part 2 | Impedance, Reflection co-efficient, Return Loss, VSWR
Jairam Gouda
Designing helical antenna in Matlab part 2 | Impedance, Reflection co-efficient, Return Loss, VSWR
10:45
Delta modulation using MATLAB Simulink | Digital Communication project
Jairam Gouda
Delta modulation using MATLAB Simulink | Digital Communication project
12:36
Designing Helical Antenna using Matlab part 1
Jairam Gouda
Designing Helical Antenna using Matlab part 1
12:20
Addition of ODD bytes 8086 microprocessor programming
Jairam Gouda
Addition of ODD bytes 8086 microprocessor programming
17:19
Interrupt INT 21H in 8086 microprocessor
Jairam Gouda
Interrupt INT 21H in 8086 microprocessor
7:32
Convert BCD to hexadecimal in 8086 microprocessor programming
Jairam Gouda
Convert BCD to hexadecimal in 8086 microprocessor programming
14:59
Conversion of Hexadecimal to BCD number | 8086 microprocessor programming
Jairam Gouda
Conversion of Hexadecimal to BCD number | 8086 microprocessor programming
22:05
Basics of 8086 microprocessors programming | String palindrome assembly level code
Jairam Gouda
Basics of 8086 microprocessors programming | String palindrome assembly level code
30:19