@ganauvm270

hello can you explain this interview question?Write Verilog DUT which counts upto 7 and then down to 0 and repeats for ever
as follows.
0,1,2,3,4,5,6,7,6,5,4,4,3,2,1
Observe that there is double 4 during down counting.
 On reset, the counter starts with a value 0
 Increments by unity on every clock upto 7
 And then decrements by unity on every clock upto 0
 But observe that during decrement number 4 repeats for two clock cycles.
Template:
module updown (
input wire clk,
input wire rst,
output reg [2:0] cnt);