@johnm2012
I welcome the return to the more sober presentation style.
@jyvben1520
SR as in set-reset, shown in the first demo with the 2 buttons
@tedbastwock3810
I don't understand the advantages of the OR, NOR, NAND latches, with 3, 8, 10 transistors, resp., over the 2-transistor latch at the beginning. I understand the features of gating, clocking, enabling, and I understand this is largely an educational video rather than a how-to video. But, in a simple circuit where one might consider a simple SR latch for use as a, say, simple solid-state switch, I don't know that the larger versions offer advantages .. but maybe they do? Obviously I'm new to this, learning, and this is something I will have to consider. I appreciate your channel very much, and wish you the best of luck with it. I like your style of presentation. Unique, well thought-out, very effective. Best regards.
@vjoh1014
Seek and you shall find Excellent young man
@KNX-Expert-ilyass
Thanks for this explain what resistance you've been used ihave problem in resistor value
@tedbastwock3810
Can we guarantee the state of SR Latch 1 on power up? I'm guessing a small ceramic capacitor between high and set (or reset?) combined with a mid-sized resistor between low and set (or reset?) might do it. I only guess because that is what guaranteed a reset on a CD4060 on power up for me.
@nikhildas5969
Thanks, your's demonstration using Transistor is very good and easy for conception. (India)
@aligunaydn9912
are the transistors bc547?
@ying6726
Very important video. Would you be able to go into permanent data storage at all?
@rawkozz8860
Hi thank you for this. Thank you. I hope you can add schematics. The circuit doesn't work on my end. Trying different resistors kinda works but ultimately the LED slowly starts to die out.
@atom1kcreeper605
Very useful information
@ArneChristianRosenfeldt
I still find it hard to imagine that we insert a flip-flop in every stage of a pipeline ( for each bit ). How much latency does it add? How is this never transparent? Isn’t there some fine tuning between these properties?
@nirnayghosh7038
if start the sr latch with s=0 r=0 then the output is q=0 and q'=1 why?? there is no previous input was there ? how it decides which output go high and which one low?
@jeffh3833
I am now building a binary counter, and I have a question about the SR latches built with logic gates. My understanding of SR latches is that there is an "invalid" state in which both inputs being high will result in both Q and Q' being low. However, I am finding that the only one I am able to build so far that includes this "invalid" state is the one constructed with NOR gates. When I use NOT and NAND gates, I do get a correctly functioning SR latches except when both inputs are high, both outputs are also high. Is this something to be concerned about?
@Linrox
I think i would understand this better if you used a component schematic, not a gate schematic.
@AakarshAnand-iq5hv
can u show how to make it and make a tutorial
@nikhildas5969
Pl, Demonstrate using Transistor the SISO 'D' FF shift register.(India)
@its_eoraptor99