@tedbastwock3810

I don't understand the advantages of the OR, NOR, NAND latches, with 3, 8, 10 transistors, resp., over the 2-transistor latch at the beginning. I understand the features of gating, clocking, enabling, and I understand this is largely an educational video rather than a how-to video. But, in a simple circuit where one might consider a simple SR latch for use as a, say, simple solid-state switch, I don't know that the larger versions offer advantages .. but maybe they do? 

Obviously I'm new to this, learning, and this is something I will have to consider. I appreciate your channel very much, and wish you the best of luck with it. I like your style of presentation. Unique, well thought-out, very effective. Best regards.

@tedbastwock3810

Can we guarantee the state of SR Latch 1 on power up?  I'm guessing a small ceramic capacitor between high and set (or reset?) combined with a mid-sized resistor between low and set (or reset?) might do it. I only guess because that is what guaranteed a reset on a  CD4060 on power up for me.

@Linrox

I think i would understand this better if you used a component schematic, not a gate schematic.