04.07.01.Describe Sync and Async DFF and Sim

Describe Sync and Async DFF in Verilog and sim it using Verilator.

Digital IC/FPGA Design Series Part 2: Verilog Language for Design and Verification
Consistency between circuit diagram, RTL code and waveform.

Go deep on Udemy:
Chapter 3: Common Used Hardware Architectures: www.udemy.com/course/digital-icfpga-design-p3commo…

Chapter 4: STA && DC Synthesis: www.udemy.com/course/digital-icfpga-design-p4-sta-…

Wish you will like it.