Creating the Layout of an Inverter using Cadence Virtuoso: VLSI Systems Lab Series 3b

This is a 3 part video series. In these 3 parts, we’ll guide you through the process of creating the symbolic view from schematic view of an inverter, create layout for a CMOS inverter using Cadence Virtuoso and perform important checks. This tutorial is perfect for beginners or those looking to sharpen their skills in custom IC design. You’ll learn how to place NMOS and PMOS transistors, connect them properly, and run important verification checks like Design Rule Check (DRC) and Layout vs. Schematic (LVS). We’ll also cover parasitic extraction and post-layout simulation to optimize the design. Join us as we continue our VLSI Systems Lab series!

Topics Covered:
-Creating a symbol view from schematic of an inverter
-Placing and connecting NMOS and PMOS transistors
-Design Rule Check (DRC) and Layout vs. Schematic (LVS)
-Parasitic extraction and post-layout simulation

Whether you're a student or a professional, this tutorial will help you master essential layout skills for VLSI design.