1 Vivado Execution of 4 BIT ADDER Verilog + Test Bench Explained With Notes 6th Sem VLSI ECE VTU

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VLSI:   • VLSI Design and Testing 6th Sem  

Embedded Systems:   • Embedded System 6th Sem  

Time Stamps:
00:00 Syllabus
03:00 4 BIT ADDER Verilog Code
08:30 4 BIT ADDER Test Bench Code
10:14 Execution of 4 BIT ADDER (Procedure)
18:05 Waveform of 4 BIT ADDER

Your Queries:
✅ Experiments Included:
• 4-bit Adder
• 4-bit Shift and Add Multiplier
• 32-bit ALU using Case & If
• D, SR, JK Flip-Flops
• 4-bit MOD-N Synchronous Counter
• CMOS Inverter – Schematic & Layout
• 2-input NOR Gate – Schematic & Layout
• Boolean Logic Y = AB+CD+E – CMOS Implementation
• Common Source Amplifier – Schematic & Layout
• Two-Stage Operational Amplifier – Full Design Flow

Tools Used: Vivado, Cadence (or equivalent), Simulation, Synthesis, DRC, LVS
Ideal for VTU students, ECE projects, and VLSI learners!